The present invention is directed to semiconductor devices, and more particularly to sense amplifier organization for semiconductor memory devices.
In semiconductor memory devices, such as a dynamic random access memory (DRAM) device, sense amplifiers are used to read data from a memory storage cell by evaluating the charge in the storage cell. FIG. 1 shows an exemplary prior art sense amplifier organization for a DRAM device. There are a plurality of wordlines (WLs) 10 and a plurality of bitlines (BLs) 20 that form a memory array 25. At the intersection of certain WLs 10 and certain BLs 20 there are storage cells 30. Sense amplifiers 40 are connected to the BLs 20 to detect a difference between the voltages on the two bitlines caused by the charge in the storage cells 30. FIG. 1 shows a folded bitline configuration, as an example.
In a one-transistor one-capacitor memory device, each WL 10 activates the access transistor (not shown) of a single storage cell. In a so-called “twin cell” organization, two storage cells 30 are used to store a charge that together represent a single bit, e.g., a “1,0”=logic “0” and “0,1”=logic “1”. One way to realize the twin cell is to combine two standard storage cells. To do this in the memory structure shown in FIG. 1, it is necessary to activate two WLs in order to access each storage cell of the twin cell because the cells are on two different WLs, as shown by the exemplary twin cell pair at reference numeral 50.
It is desirable to reduce the number of wordlines that need to be activated and to reduce the silicon area required for sense amplifiers in a semiconductor memory device that uses the twin cell architecture.